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DuttPanchal04/README.md
Typing SVG

       

👨‍💻 About Me

module DuttPanchal (

    input  wire  passion,        // VLSI & Semiconductors
    input  wire  curiosity,      // AI Agents & Automation
    output reg   impact

);

    // B.Tech ECE — Dharmsinh Desai University (DDIT), Nadiad | Batch 2026
    // Diploma ECE — BBIT, Vallabh Vidhyanagar
    // Ex-VLSI Verification Intern @Scaledge
    // Ex-VLSI Design Verification Trainee @SuchiLogic
    // Worked on AI-Assisted RTL Design and Verification
    // Email: dattpanchal2904@gmail.com

endmodule
  • 🎓 B.Tech ECE — Dharmsinh Desai University (DDIT), Nadiad · 2026 Graduate
  • 📜 Diploma ECE — Bhailalbhai & Bhikhabhai Institute of Technology (BBIT), Vallabh Vidhyanagar
  • 🏢 Ex-VLSI Verification Intern @Scaledge
  • 🏢 Ex-VLSI Verification Trainee @SuchiLogic
  • 🔬 Core domain: VLSI Design Verification, Semiconductors, RTL, CMOS & FPGA
  • 🤖 Passionate about AI Agents, AI Automation & Intelligent Workflows
  • 📜 Certified in Google Gen AI · LinkedIn Learning Gen AI
  • 📍 Nadiad, Gujarat, India · 📧 dattpanchal2904@gmail.com

🛠️ Skills & Tools

Hardware Design Languages

Verilog SystemVerilog VHDL

Programming Languages

C C++ Python

EDA & FPGA Tools

Xilinx Vivado Icarus Verilog GTKWave Yosys EDA Playground Electric VLSI LTspice KLayout

Embedded & IoT

Arduino ESP8266 NodeMCU

AI & Automation

n8n Google Gemini Claude AI ChatGPT

Tools & Platforms

Git GitHub VS Code Linux Windows

🚀 Projects

🤖 AI Projects

Repository Description
E-Commerce AI Agent AI-powered e-commerce agent — handles product queries, recommendations & order assistance using LLMs
n8n Automation Portfolio 19 production-ready n8n workflows — YouTube summarizer, Gmail-Telegram forwarder, weather alerts, notes agent & more

🔬 VLSI & CMOS Design

Repository Description
CMOS Logic Gates Layout Full schematic, DRC-clean layout & ALS simulation of NOT, AND, OR, NAND, NOR, XOR, XNOR gates
CMOS Inverter Design Complete design, layout, simulation & verification of a CMOS Inverter using Electric VLSI
6T SRAM Cell 6-Transistor SRAM cell — schematic & DRC/LVS/ERC-passed layout, ASIC-ready design flow
2×1 MUX — CMOS Transmission Gate & Pure CMOS logic MUX designs, compared side-by-side
3-Stage Ring Oscillator Schematic & layout of a clockless 3-stage ring oscillator
Electric VLSI Install Guide Step-by-step guide to install & run Electric VLSI on any OS

⚡ RTL & FPGA

Repository Description
RTL Design & Synthesis RTL-to-gate-level synthesis using Icarus Verilog, Yosys & GTKWave — inverter, ALU, MUX, counter & more
Digital Design Projects — Verilog Logic gates, combinational & sequential circuits, FIFO, FSM, RAM — all tested on EDA Playground
Dual Port RAM — Verilog 16×8 Dual-Port RAM: single clock → dual clock → $test$plusargs in 3 progressive versions
Carry Skip Adder — FPGA 2-bit CSKA synthesized & deployed on FPGA using Xilinx Vivado

🌐 Embedded & IoT

Repository Description
IoT Smart Home Automation ESP8266 NodeMCU curtain controller — remote operation via Blynk / web interface
Water Level Indicator BC547-transistor based water level monitor with LED + buzzer multi-level alerts

📊 GitHub Stats

📈 Contribution Graph

📜 Certifications

  • 🥇 Google Gen AI Certificate — Google
  • 🥇 Gen AI Certificate — LinkedIn Learning

📬 Let's Connect

     

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  1. ecommerce-ai-customer-support-revenue-protection-agent ecommerce-ai-customer-support-revenue-protection-agent Public

    A multi-agent e-commerce customer support system built using Google ADK and Gemini. Protects revenue with real-time intent classification, database validations, and fraud checks, logging via Google…

    Python

  2. n8n-ai-automation-portfolio n8n-ai-automation-portfolio Public

    A curated portfolio of production-ready, sanitized n8n workflow templates. It showcases advanced integrations of AI agents, RAG pipelines, MCP registries, and productivity automations across platfo…

  3. ambient-expense-ai-agent ambient-expense-ai-agent Public

    An ambient, event-driven expense approval AI agent built with Google ADK 2.0 and FastAPI. It automatically routes expenses, redacts PII, and protects against prompt injections by triggering human-i…

    Python

  4. Synchronous-FIFO-Design-in-Verilog Synchronous-FIFO-Design-in-Verilog Public

    This project implements an **8-depth, 8-bit wide Synchronous FIFO (First-In First-Out)** memory buffer in **Verilog HDL**. FIFO is a fundamental memory structure used widely in digital systems to h…

    SystemVerilog 1 1

  5. Digital-Design-Projects-in-Verilog Digital-Design-Projects-in-Verilog Public

    This repository contains a collection of digital design projects developed in Verilog HDL. These projects were initially written, tested, and simulated on EDA Playground, a web-based IDE for hardwa…

    SystemVerilog 6 1

  6. rtl-design-and-synthesis-using-icarus-verilog-gtkwave-yosys rtl-design-and-synthesis-using-icarus-verilog-gtkwave-yosys Public

    A collection of Verilog-based RTL design projects with testbenches, simulated using Icarus Verilog and GTKWave. This repo showcases foundational digital logic circuits as part of my VLSI learning j…

    Verilog 6