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Add RISC-V 64 Support for LuaJIT v2.1#236

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Add RISC-V 64 Support for LuaJIT v2.1#236
IgnotaYun wants to merge 21 commits into
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IgnotaYun:v2.1-riscv64

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@IgnotaYun

@IgnotaYun IgnotaYun commented Jun 27, 2024 •
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This set of patches adds support for RV64G LP64D on Linux, with full interpreter and JIT support.

Patch ported from PLCT LuaJIT, tested with LuaJIT/LuaJIT-test-cleanup.

See also upstream pr LuaJIT/LuaJIT#1267

@IgnotaYun

IgnotaYun commented Jun 27, 2024

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Oops, seems we have some issues with amd64 target……

@IgnotaYun

IgnotaYun commented Jun 27, 2024

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Oops, seems we have some issues with amd64 target……

Should have been fixed.

@IgnotaYun IgnotaYun mentioned this pull request Jun 27, 2024
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@IgnotaYun IgnotaYun force-pushed the v2.1-riscv64 branch 3 times, most recently from b2c6b14 to 74fe9b0 Compare July 3, 2024 14:09
@LocutusOfBorg LocutusOfBorg mentioned this pull request Nov 2, 2024
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@mengzhuo

mengzhuo commented Nov 3, 2024

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Can we rerun Travis CI?
Alpine using this package for LuaJit2

@IgnotaYun

IgnotaYun commented Nov 3, 2024

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Can we rerun Travis CI?

Alpine using this package for LuaJit2

I'll do a patch refresh soon.

Btw, I'm considering dropping DynASM call pseudo in favor of "PLT inline" as it's more performant and less hacky.

@IgnotaYun

IgnotaYun commented Nov 3, 2024

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Can we rerun Travis CI? Alpine using this package for LuaJit2

Done, all passing.

@mengzhuo

mengzhuo commented Nov 8, 2024

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@zhuizhuhaomeng PTAL, thanks

@IgnotaYun IgnotaYun force-pushed the v2.1-riscv64 branch 3 times, most recently from cac9628 to 59e9671 Compare November 23, 2024 10:56
@yuzibo

yuzibo commented Nov 29, 2024

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Thanks for the work!

Debian luajit has supported riscv64 based on the patch. This fixed almost >30 build dependency issues. So far, there have been no reports of build failures or test failures.

@IgnotaYun IgnotaYun force-pushed the v2.1-riscv64 branch 5 times, most recently from 4e7448d to 887b468 Compare January 18, 2025 07:00
@IgnotaYun IgnotaYun force-pushed the v2.1-riscv64 branch 2 times, most recently from 3a2022a to ea214b2 Compare January 23, 2025 06:38
@BKPepe

BKPepe commented Oct 6, 2025

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@zhuizhuhaomeng Could you please take a look? 😇

@BKPepe BKPepe mentioned this pull request Oct 6, 2025
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@glaubitz

glaubitz commented Oct 7, 2025

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Is there a chance this can be reviewed?

@IgnotaYun

IgnotaYun commented Oct 7, 2025

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Is there a chance this can be reviewed?

Ultimately, it depends on upstream opinion (i.e., Mike).

I am currently employed full-time at PLCT Lab. As Mike focuses on version 3.0, we will ensure that a functional fork for version 2.1 is available.

@andreas-schwab

andreas-schwab commented Jun 15, 2026

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Thanks, I can confirm that this fixes the problem.

@peterwillcn peterwillcn mentioned this pull request Jun 15, 2026
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@IgnotaYun IgnotaYun force-pushed the v2.1-riscv64 branch 2 times, most recently from f8b9fbb to 8f5c498 Compare June 16, 2026 09:12
@IgnotaYun

IgnotaYun commented Jun 16, 2026

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Bumped to LJRV 1ce02dd, based-off OpenResty LuaJIT v2.1-20260606.

bmwiedemann pushed a commit to bmwiedemann/openSUSE that referenced this pull request Jun 17, 2026
@bmwiedemann
Update luajit to version 2.1.20250826 / rev 21 via SR 1359644
a0c2a3e 
https://build.opensuse.org/request/show/1359644
by user mcepl + anag_factory
- riscv64-support.patch: apply bugfix from
  openresty/luajit2/pull/236#issuecomment-4706366520
IgnotaYun and others added 21 commits July 8, 2026 15:39
@IgnotaYun
riscv(support): add RISC-V 64 arch base definition
5cd5eb4
@IgnotaYun
riscv(dynasm): add RISC-V support
5fe1a5d
@IgnotaYun
riscv(interp): add register definition
20c4a97
@IgnotaYun
riscv(interp): add frame definition
6fa2bdb
@IgnotaYun
riscv(interp): add helper macros and typedefs
628fec3
@IgnotaYun
riscv(interp): add base assembly interpreter VM
d212e53
@IgnotaYun
riscv(support): add target definition
9e4395f
@IgnotaYun
riscv(ffi): add call convention and support framework
719d991
@IgnotaYun
riscv(support): add extension detection
b8e893a
@IgnotaYun
riscv(jit): add mandatory constants
c80a59d
@IgnotaYun
riscv(jit): add insn emitter
a0b77c2
@IgnotaYun
riscv(jit): add IR assembler
45e6733
@IgnotaYun @xypron
riscv(interp): add VM builder support
a51bbb0 
Co-authored-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
@IgnotaYun
riscv(misc): add bytecode listing support
e0cfa82
@IgnotaYun
riscv(jit): add hooks in interpreter
6692473
@IgnotaYun
riscv(interp): add DWARF info
45b6b83
@IgnotaYun
riscv(jit): add GDBJIT support
9505aa0
@IgnotaYun
riscv(support,linux): add Linux specfic icache sync codepath
cbaf1d0
@IgnotaYun
riscv(support,linux): make mremap() non-moving due to VA space woes
b7dad69
@IgnotaYun
riscv(misc): add disassmbler support
0032cb2
@IgnotaYun
riscv(misc): add support in Makefile
e00e8aa
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7 participants

@IgnotaYun @mengzhuo @yuzibo @BKPepe @glaubitz @peterwillcn @andreas-schwab